It is common in computer processor design to incorporate cache storage to provide memory access in less cycles than accessing main memory storage. Existing cache designs employ interleaved doublewords. From evaluation of performance and program instruction execution traces it has been found that there are many cases where multiple simultaneous requests are made to the same doubleword in the cache. To enable maximum execution rates requires the simultaneous cache access to the same doubleword. Thus, techniques are needed to efficiently handle simultaneous requests made to the same doubleword in the cache.